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Re: how do I add a D-FlipFlop to vivado block design?

Category:DefaultRelease time:-0001-11-30Views:130

Hi, I want to add a D-FlipFlop to the block diagram in vivado but i don't find it  in the IP catalog; Someone help me ? Thanks HoussemHi Houssem, You can achieve it by creating custom IP. Check this tutorial for creating and packing an IP:http://www.[More]

EFB parameter

Category:DefaultRelease time:-0001-11-30Views:130

Hi, We have a requirement that service order (SV document class) can not be create with a purchase requisition but in PO (NB document class) is mandatory. In SPRO we set the EFB parameters for selection field NBF (is used for PO, not for service orde[More]

Is it safe to convert vivado generated Kintex 7 .bit file into SVF file with ISE14.7 Impact?

Category:DefaultRelease time:-0001-11-30Views:130

Hi, I need to configure Kintex 7 chips in our system with SVF files (they will be accessible via SVF capable hardware only). Unfortunately Vivado doesn't support generation of SVF files (yet?). It seems, that I can convert the .bit file generated by[More]

Unable to create a new hardware platform in SDK from Vivado

Category:DefaultRelease time:-0001-11-30Views:130

I have exported a simple Vivado 2015.1 Hardware design to SDK 2015.1. I then open SDK to the correct workspace and take the following steps: 1) File -> New -> Application Project 2) I then name the project and click "New..." to choose the[More]

How to use spirit:componentGenerators with Vivado?

Category:DefaultRelease time:2015-10-11Views:130

Hi, I'm trying to use <spirit:componentGenerators> with Vivado, but aren't very successful at it. Unfortunately I don't have any other IP-XACT DE nor any existing core that uses it as reference. This makes it rather hard to get started.. As a simple[More]

Impossible to program a Kintex-7 with Vivado Lab Edition 2015.[1,2]

Category:DefaultRelease time:2015-10-11Views:130

Hello, I'm trying to program a Kintex-7 160T with a Platform USB Cable and Vivado Lab Edition 2015.1 and 2015.2. The JTAG chain is shown on the screenshot below: It is possible to program very small bitstream (~600KiB). But when the bitstreams become[More]

Vivado simulator is hanging

Category:DefaultRelease time:-0001-11-30Views:130

Hi, I began to learn VHDL, because in the nearer future, I will program a FPGA. At first, I started with ISE. From a tutorial, I got this program:  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity TestLED is     Port ( clk[More]

Vivado 2013.4 ERROR: [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order

Category:DefaultRelease time:-0001-11-30Views:130

Hello, I just downloaded and installed Vivado 2013.4 on my Xubuntu 12.04 machine. But when I try to add IP from the IP catalog, as in the ug937 Lab1 step2, it fails with obscure error messages (see below). Here's basically what I did: -In the Flow Na[More]

Unable to connect to hardware target in Vivado

Category:DefaultRelease time:-0001-11-30Views:130

I have Vivado 2015.1 running on Ubuntu Linux 64-bit with a Nexys4 DDR board. I've got the board set up to be programmed using the JTAG (see attached image). Running dmesg on the Linux system I see: [99537.226929] usb 1-1.2: Product: Digilent USB Devi[More]

Creating IP which doesn't link RTL / uses netlist

Category:DefaultRelease time:-0001-11-30Views:130

Hi, I created IP for my project in Vivado and it contains the source code.  I am looking for a way of creating IP where it is just a netlist and doesn't have the source code linked (so I can give it to third parties to use without them knowing the so[More]

Simulation error : size mismatch in mixed language port association with VIVADO simulator

Category:DefaultRelease time:-0001-11-30Views:130

Hi, I have instantiated a VHDL module in  a verilog top file . When I tried to simulate the verilog top , I received the following error . ERROR : Size mismatch in mixed language port association , vhdl port  vid_data (Simulation tool : VIVADO simula[More]

Vivado tcl command for design run export to spreadsheet

Category:DefaultRelease time:-0001-11-30Views:130

Hi Xilinx Vivado Gurus, Is there an easy way to run the "Export to Spreadsheet..." command inside "Design Runs" tab from TCL? Or better yet, is there a simple TCL way to summarize the results of a Vivado Synthesis / Implementation Swee[More]

Generate device tree Vivado/SDK/HSI 2015.2

Category:DefaultRelease time:-0001-11-30Views:130

1) Clone git://github.com/Xilinx/device-tree-xlnx.git to device-tree-xlnx 2) Export Hardware from vivado 2015.2 3) Launch SDK 2015.2 4) Add cloned device-tree-xlnx folder to repositories in SDK 2015.2 5) From SDK, File->New->Board Suppor Package. Se[More]

Vivado 2015.1 invalid ip core instantiation

Category:DefaultRelease time:-0001-11-30Views:130

Hi, I have an IP Core called Arbiter. It has a configuration parameter FFT_SIZE. When i create a project using tcl generated from Vivado->Export Block Design it goes with no errors. # Create instance: Arbiter_0, and set properties   set Arbiter_0 [ c[More]

"[Shape Builder 18-119]Failed to create BSCAN shape" when use ILA in IBERT example design

Category:DefaultRelease time:-0001-11-30Views:130

Hi all, I am using Vivado 2015.2. And I want to use ILA in the IBERT example design to check some nets. But when I start implementation, I get these critical warnings: [Shape Builder 18-119] Failed to create BSCAN shape for instance u_ibert_core/inst[More]

Vivado 2015.1 PS7-GMII EMIO broken. Solution inside!

Category:DefaultRelease time:-0001-11-30Views:130

Hi, I have found a huge bug in Vivado 2015.1 when using PS7 GMII on EMIO in a BD design. It is impossible to use the PS7 ENET with routing the GMII through EMIO. The problem is thet ENET0_GMII_TXD ENET0_GMII_TXEN and ENET0_GMII_TXER is permanently se[More]

Clocking Wizard broken in Vivado 2015.2?

Category:DefaultRelease time:-0001-11-30Views:130

Because I'm lazy and I didn't want to compute the PLL/MMCM parameters by hand (some kind of online calculator would be a great tool IMHO), I started up the GUI mode of Vivado 2015.2 and wanted to use the Clocking Wizard IP (which I remebered would do[More]

Vivado 2015.1 Simulator does not launch

Category:DefaultRelease time:-0001-11-30Views:130

Hi, Recently I've installed Vivado tool after downloading from xilinx website. Whenever I want to run the "Run Behavioral Simulation" after creating a testbench, messages is displayed as below but the simulator doesn't launch. I am net to this t[More]

Create HDL Library with IP Packager

Category:DefaultRelease time:-0001-11-30Views:130

I have two VHDL source files that I'm trying to package up as an IP in Vivado 2015.1.  file1.vhd contains code for a component design that will be the top-level for the IP, and file2.vhd contains code for sub-components that are instantiated in file1[More]

Vivado 2014.2 MMCM and BUFGMUX multiple syncronous clock

Category:DefaultRelease time:-0001-11-30Views:130

Hi, I am working on KC705 and I use Vivado 2014.2. The block diagram of the clocking structure and the system as below. I generated 3 clocks (250 MHz, 125 MHz, 62.5 MHz) from the input clock (250 MHz).  Because of the BUFG-BUFG error I select clockin[More]

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